1. Field of the Invention
This invention relates to computer systems, and more particularly, to impedance matching mechanisms for systems that configured for multiple processors but having one or more processors not installed.
2. Description of the Related Art
Many computer systems, such as server systems, include system boards that are configured to support multiple processors. Such computer systems typically include multiple connectors (e.g. zero-insertion force, or ZIF sockets) to accommodate the multiple processors. In addition, computer systems configured for multiple processors may include multiple bus bridges and peripheral interfaces that may be intended to be dedicated to a single one of the processors when multiple processor are installed. This may greatly increase system throughput.
Although many systems are configured to support multiple processors, such systems are often times shipped with only a single processor, or with fewer processors than the maximum number that the system is configured to accommodate. In many such computer systems, the I/O buses are coupled to the one or more processors by a single bus bridge. Thus, any processor that is in the system may utilize all of the built-in I/O capability. Furthermore, systems shipped with one or more processors not installed may still utilize the full I/O bandwidth regardless of the missing processors.
In contrast to the I/O subsystems described above, some newer I/O systems may not employ a single bus bridge. These I/O subsystems may utilize a distributed architecture including one or more bus bridges, or I/O nodes. These I/O nodes may be connected to a single processor. The processor to which each I/O node is connected may utilize the I/O bandwidth provided by the connected I/O node. Thus, a system having multiple I/O nodes, each connected to a single processor, may efficiently utilize a very large amount of I/O capability. In computer systems employing such a distributed I/O architecture, a processor missing from one of the processor slots may have the effect of reducing the system I/O bandwidth.
One possible solution to prevent the potential loss of I/O bandwidth as described above would be to provide a connecting means in the slot where a processor would normally be located. Such a connecting means may provide an electrical connection between a processor and one or more I/O nodes that would otherwise be coupled to an installed processor.
One important consideration when providing a connection means is impedance matching. In order to prevent signal reflections and other adverse affects, it may be important to carefully match the impedances of signals lines that may be coupled to each other by a connecting means in a processor slot. Due to the clock frequencies of state-of-the-art system boards, it may be difficult to provide a connection between two buses across a processor slot. Simple pin-to-pin electrical connections may be insufficient. These pin-to-pin connections may be unable to match the impedances between the coupled signal lines. The inability to match impedances between signal lines across a processor slot may result in the inability to utilize additional I/O, or may result in the need to redesign a system board.